1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a thin film transistor (TFT) used, for example, in a display device.
2. Description of the Background Art
For example, Japanese Patent Laying-Open No. 2001-345448 discloses a conventional thin film transistor and a manufacturing method thereof The thin film transistor disclosed in this publication includes an alkali-free glass substrate, a silicon nitride film formed on the glass substrate, a polycrystalline silicon film formed on the silicon nitride film and having a channel region and a source/drain region formed in the film, a gate electrode formed with a silicon oxide film (a gate insulating film) provided on the polycrystalline silicon film being interposed, and an insulating layer implemented by an silicon oxide layer formed so as to cover the gate electrode. The insulating layer has a contact hole reaching the source/drain region formed, and a metal serving as a source/drain electrode fills the contact hole.
The polycrystalline silicon film included in the thin film transistor is formed in the steps of initially forming an amorphous silicon film on the glass substrate and thereafter polycrystallizing the amorphous silicon film by instantaneous heating using excimer laser. The polycrystalline silicon film thus obtained has a thickness of 50 nm.
An operation of the thin film transistor will now be described. When the thin film transistor is of an n-type, for example, a drain current flows between the drain region and the source region by applying a positive voltage (5V, for example) to each of the gate electrode and the drain electrode and by connecting the source electrode to the ground.
Meanwhile, Japanese Patent Laying-Open No. 2000-260731 discloses a laser heat treatment method aiming to form a polycrystalline silicon film having excellent crystallinity, in order to implement a thin film transistor attaining high mobility.
In the thin film transistor disclosed in Japanese Patent Laying-Open No. 2001-345448, the polycrystalline silicon film having the channel region and the source/drain region provided is as thin as 50 nm. Accordingly, the region through which the drain current flows at the time of operation of the thin film transistor is limited within the small-thickness film. Therefore, in the n-type thin film transistor having a gate width of 10 μm, for example, an ON current (the drain current that flows when a voltage of 5V is applied to each of the gate electrode and the drain electrode) of 0.1 mA is merely obtained, which is unsatisfactorily low.
In addition, when the polycrystalline silicon film has a small thickness, a contact hole may be formed in such a manner as to penetrate the polycrystalline silicon film in forming the contact hole in the insulating layer. Here, the source/drain electrode and the polycrystalline silicon film come in contact with each other solely along side surfaces of respective electrodes. Moreover, when the polycrystalline silicon film has a small thickness, a concentration of an impurity in the film cannot be set to a high value if destruction of crystals of the polycrystalline silicon film should be avoided at the time of ion injection. For these reasons, the thin film transistor disclosed in Japanese Patent Laying-Open No. 2001-345448 is disadvantageous in that a contact resistance between the source/drain electrode and the polycrystalline silicon film is increased.
On the other hand, when the polycrystalline silicon film with a large thickness is formed, dangling bonds in the film are increased, although the above-described problem is solved. This will cause another disadvantage of a poorer transistor characteristic. In addition, when the gate insulating film is formed to cover the polycrystalline silicon film, performance in covering the polycrystalline silicon film with the gate insulating film is deteriorated. A desired transistor characteristic cannot be obtained either.